LVDS receiver on Lattice Mach OX3 CPLD (FPGA)

In this project we designed an interface between LVDS input and 16x parallel QSPI output for a 5G radio station transmitter part. The system receives data on the LVDS input, interprets the data and selectively forwards it to the 16x transmitter circuits in parallel.

The implementation platform was selected based on timing and functional requirements of the interface. Deterministic behaviour and low latency ruled out purely software based solution, while the absence of computationally intensive processing meant that a high-end FPGA would have been unnecessarily complex and costly. The Lattice MachXO3 FPGA provided deterministic timing and parallelism, with sufficient resources for the interface logic, while keeping cost and development effort under control.

We used Lattice Diamond software to prepare the project, configure the device, generate Lattice implemented IP cores, include device specific primitives, design the logic using VHDL, perform timing analysis and generate bitstream for the device. ModelSim was used for design verification and debugging, though through on-device debugging using Reveal Analyser uncovered many discrepancies between simulation and actual on-device behaviour.

Step-by-step we followed the logic path until discovering the specific place in the design where discrepancy occurred. After finding the location, the solution was not far. The first major issue was synthesis optimization which appeared to be too aggressive, therefore removing some required signals. Re-writing the same logic using slightly different syntax fixed the problem. The other was related to Lattice's implementation of FIFO which, firstly deviated from waveform description provided in the docs, and secondly, malfunctioned in the real design in some cases. This was resolved by tweaking FIFO setting which resulted in Lattice Diamond generating different implementation of FIFO IP based on different primitive. Alternative solution would be manual implementation of FIFO based on dual port RAM.

Although FPGA development is conceptually different from software development, the design itself is often quite straightforward. The real challenge is working with complex toolchains, incomplete documentation, and device-specific limitations. Successful FPGA development therefore requires patience, experience, and a systematic approach to debugging.