Parallel Lossless Compression On Xilinx Zynq UltraScale+ FPGA
Image sensors have several LVDS pairs over which they transfer image data to a recipient. In case of high speed image sensors only FPGAs and ASICs are capable of accepting data at such high rates. Sampling of data needs to be centered individually per LVDS channel and aligned across all LVDS channels FPGA, before data can be interpreted as pixel value.
Image sensors such as Gpixel GMAX2505 generate data at rates as high as 30 Gbit/s, effectively generating 3.75 GB of data every second. In such cases memory capacity and transmission channel quickly become a bottleneck, therefore framerate needs to be decreased even though image sensor and FPGA reception part are capable of running at full bitrate.
Image compression addresses this issue by effectively decreasing the amount of data used to carry the same amount of information. In case of medical and scientific applications it is also important to keep all information, therefore compression needs to be lossless.
For a high speed camera engineering and manufacturing company Optomotive we developed a parallel lossless compression IP core for Zynq UltraScale+ FPGA device running at 320 MHz and capable of compressing data at rates up to 40 Gbit/s with 16 pixels in parallel.
This work has been documented and published in a scientific journal MIPI Sensors: Parallel Lossless Compression of Raw Bayer Images on FPGA-Based High-Speed Camera.
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